ARM Cortex-M3 User Manual

Glossary
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Glossary-9
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Microprocessor See Processor.
Monitor debug-mode
One of two mutually exclusive debug modes. In Monitor debug-mode the processor
enables a software abort handler provided by the debug monitor or operating system
debug task. When a breakpoint or watchpoint is encountered, this enables vital system
interrupts to continue to be serviced while normal program execution is suspended.
See also Halt mode.
MPU See Memory Protection Unit.
Multi-layer An interconnect scheme similar to a cross-bar switch. Each master on the interconnect
has a direct link to each slave, The link is not shared with other masters. This enables
each master to process transfers in parallel with other masters. Contention only occurs
in a multi-layer interconnect at a payload destination, typically the slave.
Nested Vectored Interrupt Controller (NVIC)
Provides the processor with configurable interrupt handling abilities.
NVIC See Nested Vectored Interrupt Controller.
Penalty The number of cycles in which no useful Execute stage pipeline activity can occur
because an instruction flow is different from that assumed or predicted.
PFU See Prefetch Unit.
PMU See Power Management Unit.
Power Management Unit (PMU)
Provides the processor with power management capability.
Power-on reset See Cold reset.
PPB See Private Peripheral Bus.
Prefetching In pipelined processors, the process of fetching instructions from memory to fill up the
pipeline before the preceding instructions have finished executing. Prefetching an
instruction does not mean that the instruction has to be executed.
Prefetch Abort An indication from a memory system to the core that an instruction has been fetched
from an illegal memory location. An exception must be taken if the processor attempts
to execute the instruction. A Prefetch Abort can be caused by the external or internal
memory system as a result of attempting to access invalid instruction memory.
See also Data Abort, Abort.
Prefetch Unit (PFU) The PFU fetches instructions from the memory system that can supply one word each
cycle. The PFU buffers up to three word fetches in its FIFO, which means that it can
buffer up to three 32-bit Thumb instructions or six 16-bit Thumb instructions.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit