ARM Cortex-M3 User Manual

Programmer’s Model
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 2-9
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Base register update in LDM and STM operations
There are cases when an LDM or STM updates the base register:
• When the instruction specifies base register write-back, the base register changes
to the updated address. An abort restores the original base value.
• When the base register is in the register list of an LDM, and is not the last register
in the list, the base register changes to the loaded value.
An LDM/STM is restarted rather than continued if:
• the LDM/STM faults
• the LDM/STM is inside an IT.
If an LDM has completed a base load, it is continued from before the base load.
Saved xPSR bits
On entering an exception, the processor saves the combined information from the three
status registers on the stack. The stacked xPSR also contains information about whether
the stack was 8-byte aligned or not depending on the value of STKALIGN in the
Configuration Control Register. This information is stored in bit [9] of the xPSR on the
stack, and it is a 1 if the stack was forced to be 8-byte aligned.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit