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ARM Cortex-M3

ARM Cortex-M3
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ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 5-1
Unrestricted Access Non-Confidential
Chapter 5
Exceptions
This chapter describes the exception model of the processor. It contains the following
sections:
About the exception model on page 5-2
Exception types on page 5-4
Exception priority on page 5-6
Privilege and stacks on page 5-9
Pre-emption on page 5-11
Tail-chaining on page 5-14
Late-arriving on page 5-15
Exit on page 5-17
Resets on page 5-20
Exception control transfer on page 5-24
Setting up multiple stacks on page 5-25
Abort model on page 5-27
Activation levels on page 5-32
Flowcharts on page 5-34.

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