EasyManuals Logo

ARM Cortex-M3 User Manual

ARM Cortex-M3
410 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #206 background imageLoading...
Page #206 background image
Memory Protection Unit
9-12 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
Non-Confidential
Unrestricted Access
You cannot use these aliases to read the contents of the regions because the region
number must be written.
An example code sequence for updating four regions is
; R1 = 4 region pairs from process control block (8 words)
MOV R0, #NVIC_BASE
ADD R0, #MPU_REG_CTRL
LDM R1, [R2-R9] ; load region information for 4 regions
STM R0, [R2-R9] ; update all 4 regions at once
Note
You can normally use the
memcpy()
function in a C/C++ compiler for this sequence.
However, you must verify that the compiler uses word transfers.
9.2.4 Sub-Regions
The eight Sub-Region Disable (SRD) bits of the Region Attribute and Size Register
divide a region into eight equal-sized units based on the region size. This enables
selectively disabling some of the 1/8th sub-regions. The least significant bit affects the
first 1/8th sub-region, and the most significant bits affects the last 1/8th sub-region. A
disabled sub-region enables any other region overlapping that range to be matched
instead. If no other region overlaps the sub-region, the default behavior is used, no
match – a fault. Sub-regions cannot be used with the three smallest regions of size: 32,
64, and 128. If these sub-regions are used, the results are Unpredictable.
Example of SRD use
Two regions with the same base address overlap. One region is 64KB, and the other is
512KB. The bottom 64KB of the 512KB region is disabled so that the attributes from
the 64KB apply. This is achieved by setting SRD for the 512KB region to b00000001.

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the ARM Cortex-M3 and is the answer not in the manual?

ARM Cortex-M3 Specifications

General IconGeneral
ArchitectureARMv7-M
Instruction SetThumb-2
Pipeline Stages3-stage
InterruptsNested Vectored Interrupt Controller (NVIC)
Interrupt ControllerNested Vectored Interrupt Controller (NVIC)
Memory Protection UnitOptional
Power ConsumptionVaries by implementation
Max Clock SpeedUp to 100 MHz
DebuggingJTAG and Serial Wire Debug (SWD)
Operating Voltage1.8V to 3.6V
Manufacturing ProcessVaries by implementation
Core Type32-bit

Related product manuals