ARM Cortex-M3 User Manual

Revisions
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. B-7
Unrestricted Access Non-Confidential
SLEEPDEEP, SLEEPING, SLEEPHOLDREQ, and
SLEEPHOLDACK removed
Table A-3 on page A-4
New section added to describe the low power interface signals Low power interface signals on page A-7
New section added to describe the WIC interface signals WIC interface signals on page A-18
SLEEPHOLDACKn removed from table of miscellaneous
signals
Table A-3 on page A-4
Asserted changed to de-asserted in the description of
SLEEPHOLDREQn in table of low power interface signals
Table A-5 on page A-7
FIXMASTERTPYE added to list of AHB-AP interface signals Table A-11 on page A-13
Table B-2 Differences between issue F and issue G (continued)
Change Location

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit