Cypress FM4 Series - Default Chapter; Table of Contents

10 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
Contents
CHAPTER 1: System Overview ................................................................................................................ 23
1. Bus Architecture ............................................................................................................................ 24
1.1. Bus Block Diagram ........................................................................................................... 26
1.2. Memory Architecture ........................................................................................................ 27
1.3. Memory Map..................................................................................................................... 28
1.4. Peripheral Address Map ................................................................................................... 29
2. Cortex-M4F Architecture ................................................................................................................ 32
2.1. Option configuration ......................................................................................................... 35
3. Mode.............................................................................................................................................. 36
CHAPTER 2-1: Clock ................................................................................................................................. 37
1. Clock Generation Unit Overview .................................................................................................... 38
2. Clock Generation Unit Configuration/Block Diagram ..................................................................... 39
3. Clock Generation Unit Operations ................................................................................................. 44
3.1. Selecting the clock mode .................................................................................................. 44
3.2. Internal bus clock frequency division control .................................................................... 45
3.3. PLL clock control .............................................................................................................. 46
3.4. Oscillation stabilization wait time ...................................................................................... 48
3.5. Interrupt Factors ............................................................................................................... 49
3.6. Clock Gear function .......................................................................................................... 50
4. Clock Setup Procedure Examples ................................................................................................. 52
5. List of Clock Generation Unit Registers ......................................................................................... 58
5.1. System Clock Mode Control Register (SCM_CTL) ........................................................... 59
5.2. System Clock Mode Status Register (SCM_STR) ............................................................ 61
5.3. Base Clock Prescaler Register (BSC_PSR) ..................................................................... 62
5.4. APB0 Prescaler Register (APBC0_PSR) ......................................................................... 63
5.5. APB1 Prescaler Register (APBC1_PSR) ......................................................................... 64
5.6. APB2 Prescaler Register (APBC2_PSR) ......................................................................... 65
5.7. Software Watchdog Clock Prescaler Register (SWC_PSR) ............................................. 66
5.8. Trace Clock Prescaler Register (TTC_PSR) .................................................................... 67
5.9. Clock Stabilization Wait Time Register (CSW_TMR) ....................................................... 68
5.10. PLL Clock Stabilization Wait Time Setup Register (PSW_TMR) .................................... 69
5.11. PLL Control Register 1 (PLL_CTL1) ............................................................................... 70
5.12. PLL Control Register 2 (PLL_CTL2) ............................................................................... 71
5.13. Debug Break Watchdog Timer Control Register (DBWDT_CTL) ................................... 72
5.14. Interrupt Enable Register (INT_ENR) ............................................................................. 73
5.15. Interrupt Status Register (INT_STR) .............................................................................. 74
5.16. Interrupt Clear Register (INT_CLR) ................................................................................ 75
5.17. PLL Clock Gear Control Register (PLLCG_CTL) ............................................................ 77
6. Clock Generation Unit Usage Precautions .................................................................................... 79