Cypress FM4 Series - Methods for Controlling the Programmable CRC; Control Flow for the Programmable CRC (During Input Data Transfer from CPU)

CHAPTER 19: Programmable CRC
936 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
3. Methods for Controlling the Programmable CRC
This section explains an example of methods for controlling the programmable CRC.
3.1 Control Flow for the Programmable CRC (during Input Data Transfer
from CPU)
Figure 3-1 shows a flowchart of the control method when transferring input data from CPU to acquire
the CRC computing result. The numbers shown in the figure correspond the numbers of the following
descriptions.
Figure 3-1 Flowchart of the Control for the Programmable CRC during Input Data Transfer from CPU
#1 Start controlling for input data transfer from CPU.
#2 and #3 Check that LOCK of the PRGCRC_CFG register is "0" and go to the next step.
#4 Initialize the programmable CRC. Set appropriate initial values to the PRGCRC_POLY register, the
PRGCRC_SEED register and the PRGCRC_FXOR register. The PRGCRC_SEED register always
performs a single writing with 32-bit width access (word access).
#5 Set the PRGCRC_CFG register. In this example, the data transfer control with LOCK polling is
performed
without using interrupts. Set CIEN="0" and CDEN="0". Always set "100000" for TEST. Set an
appropriate value for data output format.
#6 Write the input data to the PRGCRC_WR register. Perform a single writing with the access width of SZ
of the PRGCRC_CFG register or more. Writing to the PRGCRC_WR register starts the CRC
computing operation.
#1 Start
#3 LOCK==0 ?
N
#4 Configure 1
Write PRGCRC_POLY reg.
Write PRGCRC_SEED reg.
Write PRGCRC_FXOR reg.
Y
#12 End
#2 Read PRGCRC_CFG reg.
#6 Input data
Write PRGCRC_WR reg.
#8 LOCK==0 ?
N
Y
#7 Read PRGCRC_CFG reg.
#9 CRC input data left ?
#11 Get result data
Read PRGCRC_RD reg.
Y
N
#5 Configure 2
Write PRGCRC_CFG reg.
#10 Change format ?
Y
N