CHAPTER 11: DSTC
568 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
5.9 HWINT[n] Register
The HWINT[n] Register sends the HW Transfer end notification to the CPU.
Register configuration
Attribute
(applicable to all areas)
Initial value
(applicable to all areas)
Register function
The HWINT[n] (Hardware transfer interrupt) Register is a read-only register for sending the HW Transfer
end notification to the CPU. The write access to this register is ignored.
If the interrupt flag set is specified in the DES started by the HW Start, or CHRS in the DES started by the
Chain Start after the DES started by the HW Start, the HWINT[n] Register is set to "1". The HWINT[n]
Register can be cleared to "0" by writing "1" to the HWINTCLR[n] Register or issuing the standby
transition command. If the HWINT[n] Register is set to "1", the HW transfer completion interrupt signal
from the DSTC (HWINT[n]) for the NVIC is asserted.
bit[255:0] HWINT[255:0] (Hardware transfer interrupt)
Causes no operation to be executed.
Indicates that the HW Transfer started has not ended normally.
Indicates that the HW Transfer started has ended normally.
If the DSTC installed in a product supports HW-128 channels, the HWINT[255:128] bits are a reserved
area whose value is fixed at "0".
If the DSTC installed in a product supports HW-64 channels, the HWINT[255:64] bits are a reserved area
whose value is fixed at "0".
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