Cypress FM4 Series - Peripheral Clock Control Register 2 (CKEN2)

CHAPTER 2-2: Clock Gating
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 101
4.5 Peripheral Clock Control Register 2 (CKEN2)
This section explains the peripheral clock control register 2(CKEN2).
bit
31
30
29
28
27
26
25
24
Field
Reserved
QSPICK
Reserved
CECCK[1:0]
Attribute
-
R/W
-
R/W
Initial value
-
0
-
11
bit
23
22
21
20
19
18
17
16
Field
Reserved
PCRCCK
Reserved
I2SCK[1:0]
Attribute
-
R/W
-
R/W
Initial value
-
1
-
00
bit
15
14
13
12
11
10
9
8
Field
IISCCK[1:0]
ICCCK[1:0]
Reserved
SDCCK
Attribute
R/W
R/W
-
R/W
Initial value
11
11
-
0
bit
7
6
5
4
3
2
1
0
Field
Reserved
CANCK[2:0]
Reserved
USBCK[1:0]
Attribute
-
R/W*
-
R/W
Initial value
-
111*
-
00
*: For products not mounting CAN controller, Attribute is R and Initial value is 00.
[bit31:29] Reserved: Reserved bits
Write 0 to these bits.
[bit28] QSPICK: Settings for operation clock supply and gating to High-Speed Quad SPI
controller
This bit controls the operation clock supply and gating to the High-Speed Quad SPI controller function.
When this bit is set to 1, the bus clock is supplied to the High-Speed Quad SPI controller unit to use the
High-Speed Quad SPI controller function. For products to which the relevant High-Speed Quad SPI
controller unit is not mounted, do not change the relevant bit from the initial value.
When this bit is set to 0, the bus clock input to the High-Speed Quad SPI unit is gated. While the bus
clock input is gated, the functions of the High-Speed Quad SPI cannot be used.
bit
Description
0
Gates the bus clock input to High-Speed Quad SPI. (Initial value)
1
Supplies the bus clock to High-Speed Quad SPI.
[bit27:26] Reserved: Reserved bits
Write 0 to these bits.