Cypress FM4 Series - CRC Use Examples

CHAPTER 13: CRC (Cyclic Redundancy Check)
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 745
2.2 CRC Use Examples
Figure 2-2 to Figure 2-5 show CRC use examples.
Use Example 1 CRC16, Byte Input Fixed
Figure 2-2 Use Example 1 (CRC16, Byte Input Fixed, Core Byte Order : Big Endian)
//*********************************************
// CRC16 (CRC ITU-T)
// polynomial: 0x1021
// initial value: 0xFFFF
// CRCCR.CRC32: 0 //CRC16
// CRCCR.LTLEND: 0 //big endian
// CRCCR.LSBFST: 0 //MSB First
// CRCCR.CRCLTE: 0 //CRC big endian
// CRCCR.CRCLSF: 0 //CRC MSB First
// CRCCR.FXOR: 0 //CRC Final XOR off
//*********************************************
//
// Example 1-1 byte-base writing
//
// Initialization
B_WRITE (CRCCR, 0x01);
// data write 0x313233343536373839
B_WRITE (CRCIN, 0x31);
B_WRITE (CRCIN, 0x32);
B_WRITE (CRCIN, 0x33);
B_WRITE (CRCIN, 0x34);
B_WRITE (CRCIN, 0x35);
B_WRITE (CRCIN, 0x36);
B_WRITE (CRCIN, 0x37);
B_WRITE (CRCIN, 0x38);
B_WRITE (CRCIN, 0x39);
// read result
H_READ (CRCR+2, data);
// check result
assert (data == 0x29B1);
//
// Example 1-2 CRC check
//
// Initialization
B_WRITE (CRCCR, 0x01);
// data write 0x313233343536373839 + CRC
B_WRITE (CRCIN, 0x31);
B_WRITE (CRCIN, 0x32);
B_WRITE (CRCIN, 0x33);
B_WRITE (CRCIN, 0x34);
B_WRITE (CRCIN, 0x35);
B_WRITE (CRCIN, 0x36);
B_WRITE (CRCIN, 0x37);
B_WRITE (CRCIN, 0x38);
B_WRITE (CRCIN, 0x39);
B_WRITE (CRCIN, 0x29); // <-- CRC
B_WRITE (CRCIN, 0xB1); // <-- CRC
// read result
H_READ (CRCR+2, data);
// check result
assert (data == 0x0000);
(Assumed as follows)
B_WRITE -- Byte writing
H_WRITE -- Half-word writing
W_WRITE -- Word writing
B_READ -- Byte reading
H_READ -- Half-word reading
W_READ -- Word reading
CRCCR -- CRC Control Register address
CRCINIT -- Initial Value Register address
CRCIN -- Input Data Register address
CRCR -- CRC Register address
CRC computing unit input sequence image
3
1
3
2
3
3
3
9
MSB
LSB
− The byte and half-word writing positions are arbitrary. In this example, data is written continuously
at position +0.
− Table 2-1 shows the CPU, CRC result byte order, CRCR (CRC Register) output position, and read
address in CRC16 mode.
Table 2-1 CPU, CRC Result Byte Order, and CRCR Read Address
Core Byte Order
CRC Result Byte Order
Output Position to
CRCR
CRCR H_READ Address
Big endian
Big endian
bit 15 to bit 0
CRCR +2
Big endian
Little endian
bit 31 to bit 16
CRCR +0
Little endian
Big endian
bit 15 to bit 0
CRCR +0
Little endian
Little endian
bit 31 to bit 16
CRCR +2