Cypress FM4 Series - Entire DMAC Configuration Register (DMACR)

CHAPTER 10: DMAC
492 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
5.2 Entire DMAC Configuration Register (DMACR)
This section explains entire DMAC configuration register (DMACR).
bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Field
DE
DS
Reserved
PR
DH[3:0]
Reserved
Attribute
R/W
R/W
-
R/W
R/W
-
Initial Value
0
0
-
0
0000
-
bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Field
Reserved
Attribute
-
Initial Value
-
[bit31] DE : DMA Enable (all-channel operation enable bit)
This bit controls the enabling and disabling of transfer operations for all of the channels.
When "1" is set to this bit, the operations of all of the channels are enabled and each channel operates
according to its settings.
When "0" is set to this bit, the operations of all of the channels are disabled, and no transfer is performed
until "1" is set to the bit. Also, a channel in the middle of its transfer operation is forced to stop the transfer.
This bit can be used to force all of the channels that are currently performing a transfer to stop it and reset
the configuration register.
bit
Function
0
Disables the operations of all of the channels. (Initial value)
1
Enables the operations of all of the channels.
[bit30] DS : DMA Stop
This bit indicates the transfer state of all of the channels.
If either of the following conditions is established during transfer operation, the bit is set to "1" by DMAC.
− When "0" is written to the DMACR:DE bit and then the transfers of all of the channels are
completed.
− When a value other than "0000" is written to the DMACR:DH bit and then the transfers of all of the
channels pause.
When DMACR:DE=1 and DMACR:DH=0000 are set and all of the channels become enabled to operate,
this bit is set to "0" by DMAC.
Although the attribute of this bit is R/W, writing to it by CPU does not affect DMAC’s operation. If, however,
the DMACR register needs to be updated without affecting the state of this bit, first read from this bit and
then rewrite the same value.
bit
Function
0
Clears the disabling of all-channel operation or the setting of all-channel pause. (Initial value)
1
The transfers of all of the channels have stopped due to the disabling of all-channel operation
or the setting of all-channel pause.