Cypress FM4 Series - Peripheral Function Reset Control Reset 2 (MRST2)

CHAPTER 2-2: Clock Gating
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 105
4.6 Peripheral Function Reset Control Reset 2 (MRST2)
This section explains the peripheral function reset control register 2 (MRST2).
bit
31
30
29
28
27
26
25
24
Field
Reserved
QSPIRST
Reserved
CECRST[1:0]
Attribute
-
R/W
-
R/W
Initial value
-
0
-
00
bit
23
22
21
20
19
18
17
16
Field
Reserved
PCRCRST
Reserved
I2SRST[1:0]
Attribute
-
R/W
-
R/W
Initial value
-
0
-
00
bit
15
14
13
12
11
10
9
8
Field
IISCRST[1:0]
ICCRST[1:0]
Reserved
SDCRST
Attribute
R/W
R/W
-
R/W
Initial value
00
00
-
0
bit
7
6
5
4
3
2
1
0
Field
Reserved
CANRST[2:0]
Reserved
USBRST[1:0]
Attribute
-
R/W
-
R/W
Initial value
-
000
-
00
[bit31:29] Reserved: Reserved bits
Write 0 to these bits.
[bit28] QSPIRST: Reset control of High-Speed Quad SPI controller
This bit controls the reset of the Hi-Speed Quad SPI controller unit. If this bit is set to 1, the SD card
interface becomes a reset state, the operation of the High-Speed Quad SPI controller stops, and the
register settings are initialized. For products to which the High-Speed Quad SPI controller is not mounted,
do not set this bit to 1. To release the above-mentioned reset state, be sure to set this bit to 0 again.
bit
Description
0
Releases the reset of High-Speed Quad SPI controller. (Initial value)
1
Issue the reset signal to High-Speed Quad SPI controller.
[bit27:26] Reserved: Reserved bits
Write 0 to these bits.