Cypress FM4 Series - PLL Control Register 2 (PLL_CTL2)

CHAPTER 2-1: Clock
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 71
5.12 PLL Control Register 2 (PLL_CTL2)
The PLL_CTL2 sets the PLL frequency division ratio.
Register configuration
bit
7
6
5
4
3
2
1
0
Field
Reserved
PLLN
Attribute
-
R/W
Initial value
-
000000
Register functions
[bit7:6] Reserved: Reserved bits
0b00 is read from these bits.
Set these bits to 0b00 when writing.
[bit5:0] PLLN: PLL feedback frequency division ratio setting bits
bit5:0
Description
000000
The frequency division is (PLLN value +1). (Frequency division : 1 to 64)
Example: PLLN value (000000) +1 => 1/1 division [Initial value]
000001
-
-
110001
110010
-
111111
Notes:
− Set the frequency division ratio before enabling the PLL oscillation enable bit (PLLE) of the
SCM_CTL register.
− This register is not initialized by software reset.