Cypress FM4 Series - Deep Standby RAM Retention Register (DSRAMR)

CHAPTER 6: Low Power Consumption Mode
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 239
8.8 Deep Standby RAM Retention Register (DSRAMR)
The Deep Standby RAM Retention Register controls the retention of data in SRAM2 in a deep standby
mode.
Bit
7
6
5
4
3
2
1
0
Field
Reserved
SRAMR
Attribute
-
R/W
Initial value
000000
00
[bit7:2] Reserved: Reserved bits
These bits always read 0b000000.
Writing a value to these bits has no effect on operation.
[bit1:0] SRAMR: SRAM2 retention control bits
These bits control the retention of data in SRAM2 in a deep standby mode.
Bit1
bit0
Description
0
0
Data in SRAM2 is not retained in a deep standby mode. [initial value]
0
1
Setting is prohibited.
1
0
Setting is prohibited.
1
1
Data in SRAM2 is retained in a deep standby mode.
Note:
− This register is initialized by the power-on reset and the low voltage detection reset. It is not
initialized by any reset other than the two mentioned before.