Cypress FM4 Series - Interrupt Status Register (INT_STR)

CHAPTER 2-1: Clock
74 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
5.15 Interrupt Status Register (INT_STR)
The INT_STR indicates the status of interrupts.
Register configuration
bit
7
6
5
4
3
2
1
0
Field
Reserved
FCSI
Reserved
PCSI
SCSI
MCSI
Attribute
-
R
-
R
R
R
Initial value
-
0
-
0
0
0
Register functions
[bit7:6] Reserved: Reserved bits
0b00 is read from these bits.
Set these bits to 0b00 when writing.
[bit5] FCSI: Anomalous frequency detection interrupt status bit
bit
Description
0
No FCS interrupt has been asserted.
1
An FCS interrupt has been asserted.
[bit4:3] Reserved: Reserved bits
0b00 is read from these bits.
Set these bits to 0b00 when writing.
[bit2] PCSI: PLL oscillation stabilization wait completion interrupt status bit
bit
Description
0
No PLL oscillation stabilization wait completion interrupt has been asserted.
1
A PLL oscillation stabilization wait completion interrupt has been asserted.
[bit1] SCSI: Sub clock oscillation stabilization wait completion interrupt status bit
bit
Description
0
No sub clock oscillation stabilization wait completion interrupt has been asserted.
1
A sub clock oscillation stabilization wait completion interrupt has been asserted.
[bit0] MCSI: Main clock oscillation stabilization wait completion interrupt status bit
bit
Description
0
No main clock oscillation stabilization wait completion interrupt has been asserted.
1
A main clock oscillation stabilization wait completion interrupt has been asserted.