Cypress FM4 Series - IRQ059 Batch Read Register (IRQ059 MON)

CHAPTER 8: Interrupts
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 409
4.21 IRQ059 Batch Read Register (IRQ059MON)
The IRQ059 Batch Read Register (IRQ059MON) can read out at once the interrupts (main clock
oscillation stabilization wait completion interrupt, sub clock oscillation stabilization wait completion
interrupt, main PLL oscillation stabilization wait completion interrupt, and PLL of USB / Ethernet oscillation
stabilization wait completion interrupt / PLL of I
2
S oscillation stabilization wait completion interrupt / PLL of
GDC oscillation stabilization wait completion interrupt ) assigned to exception no. 75.
Register configuration
bit
31
8
Field
Reserved
Attribute
R
Initial value
0x000000
bit
7
6
5
4
3
2
1
0
Field
Reserved
GPLLINT
IPLLINT
UPLLINT
MPLLINT
SOSCINT
MOSCINT
Attribute
R
R
R
R
R
R
R
Initial value
00
0
0
0
0
0
0
Register function
[bit31:6] Reserved: Reserved bits
A reserved bit reads 0.
[bit5] GPLLINT
Value
Description
0
There is no PLL of GDC oscillation stabilization wait completion interrupt.
1
A PLL of GDC oscillation stabilization wait completion interrupt has been made.
[bit4] IPLLINT
Value
Description
0
There is no PLL of I
2
S oscillation stabilization wait completion interrupt.
1
A PLL of I
2
S oscillation stabilization wait completion interrupt has been made.
[bit3] UPLLINT
Value
Description
0
There is no PLL of USB / Ethernet oscillation stabilization wait completion interrupt.
1
A PLL of USB / Ethernet oscillation stabilization wait completion interrupt has been made.
[bit2] MPLLINT
Value
Description
0
There is no main PLL oscillation stabilization wait completion interrupt.
1
A main PLL oscillation stabilization wait completion interrupt has been made.
[bit1] SOSCINT
Value
Description
0
There is no sub clock oscillation stabilization wait completion interrupt.
1
A sub clock oscillation stabilization wait completion interrupt has been made.
[bit0] MOSCINT
Value
Description
0
There is no main clock oscillation stabilization wait completion interrupt.
1
A main clock oscillation stabilization wait completion interrupt has been made.