CHAPTER 11: DSTC
524 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
3.2.5 Arbitration of Transfer Requests
The DSTC arbitrates start triggers if multiple HW Start requests conflict with an SW Start request, and
executes transfers sequentially. The arbitration of start requests are processed by two blocks, Arbiter 1
and Arbiter 2, shown in Figure 3-5. Below are details of arbitration.
Arbiter 1
The HW transfer request is arbitrated by Arbiter 1. If there are conflicting requests, Arbiter 1 uses the
rotation method explained below to select a transfer start channel. After a bus reset, the smaller the
channel number, the higher the priority is in the selection priority order.
highest priority 0,1,2,3,4,5,6,7,,,,,,254,255 lowest priority
According to this priority order, for instance, if a request from channel 5 and another from channel 6 are
made simultaneously, channel 5 is selected. Once a transfer channel is selected, its priority is rotated to
the lowest. In the above example, as channel 5 is selected, the priority order is updated to the one below.
highest priority 6,7,8,9,10,11,,,,,,254,255, 0,1,2,3,4,5 lowest priority
According to this priority order, for instance, if a request from channel 5 and another from channel 6 are
made simultaneously, channel 6 is selected. The rotation method enables multiple HW transfer requests
to be processed equally.
Arbiter 1 refers to HWDESP[n] of channel n selected and notifies Arbiter 2 of the DESP of the DES used.
In addition, if the Chain Start is used in the HW transfer, Arbiter 1 notifies Arbiter 2 of the updated DESP.
After all Chain transfers have ended and the DSTC has started to wait for the next Start Trigger, Arbiter 1
notifies Arbiter 2 of the transfer request of the channel n selected.
Arbiter 2
Arbiter 2 selects which of the HW transfer request selected by Arbiter 1 and the SW transfer request is to
be executed. If there are conflicting transfer requests, the DSTC selects a transfer request according to
the probability set in the SWPR (Software transfer priority) bits in the CFG Register and starts the transfer
engine. Table 3-11 shows the settings of the SWPR bits in the CFG Register and the probability of the SW
transfer acquiring the transfer right.
Table 3-11 Details of CFG:SWPR[2:0]
In the arbitration of Arbiter 2, if the SW transfer request conflicts with the HW transfer request,
Arbiter 2 specifies the probability of the SW transfer acquiring the transfer right.
000: Sets the priority of the SW transfer to the highest priority. (If an SW transfer request is made
while an HW transfer is in progress, the SW transfer starts after the HW transfer has ended.)
001: Sets the probability of the SW transfer acquiring the transfer right to 1/2.
010: Sets the probability of the SW transfer acquiring the transfer right to 1/3.
011: Sets the probability of the SW transfer acquiring the transfer right to 1/7.
100: Sets the probability of the SW transfer acquiring the transfer right to 1/15. (Initial value)
101: Sets the probability of the SW transfer acquiring the transfer right to 1/31.
110: Sets the probability of the SW transfer acquiring the transfer right to 1/63.
111: Sets the priority of the SW transfer to the lowest priority. (The SW transfer starts only when
there is no HW transfer request.)
Example of Arbiter Operation
Figure 3-6 shows an operation example. The horizontal axis in the figure is the time axis. The figure
illustrates the order of granting the transfer right to different transfer requests during the arbitration by the
DSTC. There are three transfer sources: HW channel A transfer, HW channel B transfer and SW transfer.
The HW[A] transfer and the HW[B] transfer are connected in a Chain transfer by two DES; SW transfers
are connected in a Chain transfer by three DES. The SWPR bits in the CFG Register are set to 001
(probability of SW transfer: 1/2). No Chain lock is specified in any DES.
At timing (1), the respective transfer requests of HW[A] transfer, HW[B] transfer and SW transfer are
made simultaneously. Arbiter 1 arbitrates the conflict between HW[A] transfer and HW[B] transfer. Arbiter
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