CHAPTER 11: DSTC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 525
1 selects one from HW[A] transfer and HW[B] transfer according to the preceding rotation status. The
following description assumes that Arbiter 1 has selected HW[A] transfer. Arbiter 2 arbitrates the conflict
between HW[A] transfer and SW transfer. Arbiter 2 selects one from HW[A] transfer and SW transfer
according to the preceding rotation status. The following description assumes that Arbiter 2 has selected
HW[A] transfer. The transfer engine of the DSTC starts the transfer of 1st-DES of HW[A].
Figure 3-6 Example of Arbiter Operation
At timing (2), the transfer of HW[A] 1st-DES ends. A Chain Start request of HW[A] 2nd-DES is made. (The
request of HW[B] is held until there is no more Chain Start of HW[A].) Arbiter 1 requests Arbiter 2 for
2nd-DESP of HW[A]. Arbiter 2 arbitrates the conflict between HW[A] transfer and SW transfer. As the
probability for SW transfer is 1/2, and Arbiter 2 has selected HW[A] transfer at timing (1), Arbiter 2 selects
SW 1st-DES transfer.
At timing (3), the transfer of SW 1st-DES ends and the Chain Start request of SW 2nd-DES is made.
Arbiter 2 arbitrates the conflict between HW[A] 2nd-DES transfer and SW-2ndDES transfer. As the
probability for SW transfer is 1/2, and Arbiter 2 has selected SW transfer at timing (2), Arbiter 2 selects
HW[A] 2nd-DES transfer.
At timing (4), the transfer of HW[A]-2ndDES ends. Arbiter 1 makes a request for transferring HW[B]
1st-DES to Arbiter 2. Arbiter 2 arbitrates the conflict between HW[B] 1st-DES transfer and SW 2nd-DES
transfer, and then selects SW 2nd-DES transfer.
At timings (5), (6) and (7), Arbiter 2 executes the same arbitration operations and selects HW[B] 2nd-DES
transfer and SW 3rd-DES transfer.
As explained above, SW transfer may be executed during the Chain transfer of HW transfer, and HW
transfer during the Chain transfer of SW transfer. During the Chain transfer of HW transfer, no HW
transfer on any other channel is executed. If the Chain lock has been specified in the DES, regardless of
the setting of the SWPR bits in the CFG Register, after the transfer of that DES has been executed, the
transfers of the DES in the Chain Start are always executed successively.
In the above example, as the probability is set to 1/2 in the SWPR bits in the CFG Register, one SW
transfer is executed in every two transfers. Taking account of the number of HW transfer channels of the
DSTC to be used simultaneously, the number of Chains in the DES, the transfer data size in each transfer,
etc., select an appropriate value for the SWPR bits in the CFG Register. The value of the SWPR bits in
the CFG Register can be modified even when the DSTC is executing a transfer. After the value of the
SWPR bits in the CFG Register has been modified, it is applied from the next SW Start Trigger.
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