Cypress FM4 Series - DMAC Operation and Control Procedure for Hardware (EM=1) Transfer

CHAPTER 10: DMAC
486 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
4.4 DMAC Operation and Control Procedure for Hardware (EM=1) Transfer
This section explains DMAC operation and control procedure for hardware (EM=1) transfer.
Figure 4-13 Transitional Diagram of Hardware (EM=1) Transfer State
Figure 4-13 shows a transitional diagram of the states of the channel to be controlled for hardware
(EM=1) transfer. The numbers next to the transitional lines in Figure 4-13 correspond to the numbers
which appear in the following control procedures. The solid transitional lines indicate transitions of state
instructed by CPU, while the broken transitional lines indicate transitions of state due to DMAC/Peripheral
operation.
EM (Enable bit clear mask) is a bit that masks EB clear upon the completion of transfer of the channel to
be controlled. EM=1 enables the same transfer process to be repeated without giving instructions from
CPU.
2
5
,
6
,
7
4
Disable
DE=0 or EB=0 or
DH!=0000 or PB=1
initial : SS=000
after stop : SS=code
Transfer
Pause
9
,
1
0
1
0
1
,
1
1
,
1
5
Reset
1
2
1
3
1
4
Wait 1st trigger
3
1
5
8
DE=1 EB=1
DH=0000 PB=0
initial : SS=000
after stop : SS=code
DE=1 EB=1
DH=0000 PB=0
SS=000
DE=1 EB=1
DH!=0000 or PB=0
SS=111
Transition by DMAC/Peripheral
Transition by CPU