Cypress FM4 Series - Peripheral Clock Gating Overview

CHAPTER 2-2: Clock Gating
82 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
1. Peripheral Clock Gating Overview
This section shows an overview of the Peripheral Clock Gating which stops the operation clocks of
peripheral functions individually. By using these functions, the system can reduce the current
consumption of the total system with gating the operation clocks of peripheral functions not used.
Overview of Peripheral Clock Gating
 The operation clocks of peripheral functions not used in the system operation are gated individually.
 For target clocks and units of the Peripheral Clock Gating, see Gating units and their initial states of
Peripheral Clock Gating.
 When a clock is gated or before a clock is supplied, the internal states of peripheral functions can be
reset.
The above peripheral clock gating and reset control are implemented by the setting of a register
connecting to APB2 bus.