Cypress FM4 Series - Interrupt Enable Register (INT_ENR)

CHAPTER 2-1: Clock
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 73
5.14 Interrupt Enable Register (INT_ENR)
The INT_ENR enables/disables interrupts.
Register configuration
bit
7
6
5
4
3
2
1
0
Field
Reserved
FCSE
Reserved
PCSE
SCSE
MCSE
Attribute
-
R/W
-
R/W
R/W
R/W
Initial value
-
0
-
0
0
0
Register functions
[bit7:6] Reserved: Reserved bits
0b00 is read from these bits.
Set these bits to 0b00 when writing.
[bit5] FCSE: Anomalous frequency detection interrupt enable bit
bit
Description
0
Disables FCS interrupts
1
Enables FCS interrupts
[bit4:3] Reserved: Reserved bits
0b00 is read from these bits.
Set these bits to 0b00 when writing.
[bit2] PCSE: PLL oscillation stabilization wait completion interrupt enable bit
bit
Description
0
Disables PLL oscillation stabilization wait completion interrupts
1
Enables PLL oscillation stabilization wait completion interrupts
[bit1] SCSE: Sub clock oscillation stabilization wait completion interrupt enable bit
bit
Description
0
Disables sub clock oscillation stabilization wait completion interrupts
1
Enables sub clock oscillation stabilization wait completion interrupts
[bit0] MCSE: Main clock oscillation stabilization wait completion interrupt enable bit
bit
Description
0
Disables main clock oscillation stabilization wait completion interrupts
1
Enables main clock oscillation stabilization wait completion interrupts
Note:
− For Anomalous frequency detection, see Chapter Clock supervisor.