CHAPTER 11: DSTC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 563
5.6 SWTR Register
The SWTR (Software trigger) Register issues the Start Trigger of the SW Start transfer.
Register configuration
Register function
The SWTR (Software trigger) Register issues the Start Trigger of the SW Transfer if a write access to this
register is made. Use the 16-bit (halfword) access to write a value to this register. The 32-bit (word) write
access is ignored. If the SW Start instruction has been executed, and that transfer has not ended
(SWREQ ≠ 0) or the DSTC is not in the normal state (CMD ≠ 00) or the DSTC is in the error stop state
(ESTOP ≠ 0), the DSTC ignores the write access from the CPU and also the new SW Start transfer
request.
bit[29:16] SWDESP[13:0] (Software DES pointer)
Write the value of DESP of the DES to be started. The DSTC transfers data according to the DES area of
DESTP+SWDESP. If a Chain Start is executed during the SW Transfer, SWDESP is updated by the
DSTC to the value of DESP used in the Chain Start. Align DES to the word boundary. Always write "00" to
the lower 2 bits in SWDESP. SWDESP cannot be set to a value larger than "0x3FF0".
A write access to these bits specifies the DESP for transfer to be started by the SW Start.
These bits indicate the DESP for SW Start transfer that is in progress or that has been ended.
bit[30] SWREQ (Software request)
The SWREQ bit is a read-only bit indicating whether the execution of the SW Transfer is pending, or the
SW Transfer as well as the Chain Start transfer are being executed. The value written to this bit is ignored.
A write access (Start Trigger) to the SWTR Register sets the SWREQ bit to "1". If the SW Transfer ends
normally, abnormally, or is waiting for a Start Trigger, SWREQ is reset to "0".
The value written to this bit is meaningless.
Indicate that either the SW Transfer is not requested or has been ended.
Indicate that either the SW Transfer is pending or the DSTC is performing the SW Transfer.
bit[31] SWST (Software status)
The SWST bit is a read-only bit for sending the SW Transfer end notification to the CPU. The interrupt
flag set is specified in the DES of the SW Transfer. If the SW Transfer ends normally, SWST is set to "1".
SWST is cleared to "0" by the SWCLR command, the standby transition command or the write access to
the SWTR Register. In the case of (CFG:SWINTE = 1)&&(SWTR:SWST == 1), the SWINT interrupt signal
is asserted.
The value written to this bit is meaningless.
Indicates that the SW Transfer has not ended normally.
Indicates that the SW Transfer has ended normally.
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