Cypress FM4 Series - CRC Computing Input Data Register

CHAPTER 19: Programmable CRC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 949
4.6 CRC Computing Input Data Register
The CRC computing input data register (PRGCRC_WR) specifies the input data of CRC computing.
Register configuration
Address: +0x10
bit 31 0
Field
PRGCRC_WR[31:0]
Attribute
R/W
Initial value
0x 0000 0000
Register functions
[bit31:0] PRGCRC_WR (CRC input write data)
Access
Application
Write
Sets the input data of CRC computing and starts CRC computing.
Read
Reads the register setting value.
By performing write access to this register, the input data specification of CRC computing and the CRC
computing start are performed at the same time. The data of the size specified with
PRGCRC_CFG.SZ[1:0], one of the value written in this register, will be the input data to LFSR. In addition,
the input format conversion for byte order/bit order is performed by specifying PRGCRC_CFG.FI[1:0] and
the data will be input to LFSR.
Table 4-5 shows the format conversion operation of input data. It shows the relationship between the
byte/bit position of this register and order for inputting to LFSR. For example, in case of SZ="01" and
FI="01", it shows the data is captured in the order of bit[7], bit[6],,, bit[1], bit[0], bit[15], bit[14],,, bit[9], bit[8]
from write value of this register. Also it shows that the write data with * mark is ignored and has no effect
in CRC computing.
Table 4-5 Input format conversion
SZ
[1:0]
FI
[1:0]
PRGCRC_WR register write value
Address+3
Bit[31:24]
Address +2
Bit[23:16]
Address +1
Bit[15:8]
Address +0
Bit[7:0]
00
(8-bit)
0X
*,*,*,*,*,*,*,*
*,*,*,*,*,*,*,*
*,*,*,*,*,*,*,*
1,2,3,4,5,6,7,8
1X
*,*,*,*,*,*,*,*
*,*,*,*,*,*,*,*
*,*,*,*,*,*,*,*
8,7,6,5,4,3,2,1
01
(16-bit)
00
*,*,*,*,*,*,*,*
*,*,*,*,*,*,*,*
1,2,3,4,5,6,7,8
9,10,11,12,13,14,15,16
01
*,*,*,*,*,*,*,*
*,*,*,*,*,*,*,*
9,10,11,12,13,14,15,16
1,2,3,4,5,6,7,8
10
*,*,*,*,*,*,*,*
*,*,*,*,*,*,*,*
8,7,6,5,4,3,2,1
16,15,14,13,12,11,10,9
11
*,*,*,*,*,*,*,*
*,*,*,*,*,*,*,*
16,15,14,13,12,11,10,9
8,7,6,5,4,3,2,1
10
(24-bit)
00
*,*,*,*,*,*,*,*
1,2,3,4,5,6,7,8
9,10,11,12,13,14,15,16
17,18,19,20,21,22,23,24
01
*,*,*,*,*,*,*,*
17,18,19,20,21,22,23,24
9,10,11,12,13,14,15,16
1,2,3,4,5,6,7,8
10
*,*,*,*,*,*,*,*
8,7,6,5,4,3,2,1
16,15,14,13,12,11,10,9
24,23,22,21,20,19,18,17
11
*,*,*,*,*,*,*,*
24,23,22,21,20,19,18,17
16,15,14,13,12,11,10,9
8,7,6,5,4,3,2,1
11
(32-bit)
00
1,2,3,4,5,6,7,8
9,10,11,12,13,14,15,16
17,18,19,20,21,22,23,24
25256,27,28,29,30,31,32
01
25256,27,28,29,30,31,32
17,18,19,20,21,22,23,24
9,10,11,12,13,14,15,16
1,2,3,4,5,6,7,8
10
8,7,6,5,4,3,2,1
16,15,14,13,12,11,10,9
24,23,22,21,20,19,18,17
32,31,30,29,28,27,26,25
11
32,31,30,29,28,27,26,25
24,23,22,21,20,19,18,17
16,15,14,13,12,11,10,9
8,7,6,5,4,3,2,1
In case of SZ[1:0]=00, specifying FI[0] has no meaning. To perform write access to this register, perform
with single access and with access width of data size width specified for PRGCRC_CFG.SZ[1:0] or more.
An aligned access and write access divided into multiple times are not possible. Write access to this
register is not allowed when CRC computing is performed (PRGCRC_CFG. LOCK="1").