Cypress FM4 Series - Area Register 0 to Area Register 7 (AREA0 to AREA7)

CHAPTER 14: External Bus Interface
816 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
6.3 Area Register 0 to Area Register 7 (AREA0 to AREA7)
The AREA0 to AREA7 registers set the address area by CS0 to CS7.
bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Field
Reserved
MASK
Attribute
-
R/W
Initial value
-
0001111 (16MB width)
bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Field
Reserved
ADDR
Attribute
-
R/W
Initial value
-
(from MCSX[0])
00000000, 00010000, 00100000,
00110000, 01000000, 01010000,
01100000, 01110000 *1
[bit31:23]Reserved: Reserved bits
The read value is undefined.
Set this bit to 0 when writing.
[bit22:16] MASK: address mask
These bits set the value to mask [26:20] of the internal address (27:20) set in ADDR.
If 1 is set as a mask value according to the specified mask value, the external bus interface masks each
of the internal bus and ADDR, and compares the masking results. If the results are matched, the external
bus interface accesses the MCSX signal.
A bit set to 1 for masking is lost during masking process. The bit is disabled even if it is set in ADDR.
The example shown in Table 6-2 indicates the relationship between the mask setup and the address area
size.
Table 6-2 MASK Setup Value and Address Area per CS
MASK setup value
Address area per CS
111_1111
128 MB
011_1111
64 MB
001_1111
32 MB
000_1111
16 MB
000_0111
8 MB
000_0011
4 MB
000_0001
2 MB
000_0000
1 MB
[bit15:8]Reserved: Reserved bits
The read value is undefined.
Set this bit to 0 when writing.