Cypress FM4 Series - Port Output Data Register (VBDOR)

CHAPTER 7-3: VBAT Domain(B)
350 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
7.12 Port Output Data Register (VBDOR)
VBDOR Register sets the data output to pins.
In TYPE4-M4 products, the GPIO function of P46/X0A pin and P47/X1A pin is an input only, therefore the
settings of the VBDOR[3:2] are invalid.
bit
7
6
5
4
3
2
1
0
Field
Reserved
VDOR3
VDOR2
VDOR1
VDOR0
Attribute
-
R/W
R/W
R/W
R/W
Initial value
-
1
1
1
1
The interface circuit type for this register is type 3.
[bit7:4] Reserved: Reserved bits
These bits read 0b0000.
In a write access to these bits, write 0b0000 to them.
[bit3] VDOR3: Port output data of P46/X0A pin bit
[bit2] VDOR2: Port output data of P47/X1A pin bit
[bit1] VDOR1: Port output data of P49/VWAKEUP pin bit
[bit0] VDOR0: Port output data of P48/VREGCTL pin bit
bit
Description
Reading
A read access reads the value of this bit. (Initial value = 1)
Writing
0
Outputs L level to the GPIO port.
If the pin is used as an input pin or as a peripheral function I/O pin, the setting of this bit is
ignored.
1
Outputs H level to the GPIO port.
If the pin is used as an input pin or as a peripheral function I/O pin, the setting of this bit is
ignored.