Cypress FM4 Series - Division Clock Register (DCLKR)

CHAPTER 14: External Bus Interface
834 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
6.11 Division Clock Register (DCLKR)
The following shows the configuration of DCLKR.
bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Field
Reserved
Attribute
-
Initial value
-
bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Field
Reserved
MCLKON
MDIV
Attribute
-
R/W
R/W
Initial value
-
0
1111
[bit31:5] Reserved: Reserved bits
The read value is undefined.
Set this bit to 0 when writing.
[bit4] MCLKON: MCLKOUT ON
This bit is used to set the output of clock for SRAM/Flash memory (MCLKOUT) enable.
bit
Description
0
Does not output the clock for SRAM/Flash memory (MCLKOUT). [Initial value]
1
Outputs the clock for SRAM/Flash memory (MCLKOUT).
Note:
− After MCLKON is changed, check that the register read setting is changed.
[bit3:0] MDIV: MCLK /MSDCLK Division Ratio Setup
These bits are used to set the division ratio (1/1 to 1/16) of the division clock.
The division clock will be divided into (MDIV+1) division.
The division ratio specified with these bits is reflected to both SRAM/Flash memory clock (MCLKOUT)
and SDRAM clock (MADCLK).
Set the value of the division ratio in the range that meets the following conditions.
− Set the upper limit to one-half of the maximum frequency of the base clock (HCLK).
− In order to output MCLKOUT and MSDCLK from this LSI, set the division ratio that meets the output
specifications described in the Datasheet.
bit3
bit2
bit1
bit0
Description
0
0
0
0
1 division
0
0
0
1
2 division
…
…
1
1
1
1
16 division [Initial value]
Notes: