Cypress FM4 Series - VB_CLKDIV Register

CHAPTER 7-3: VBAT Domain(B)
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 337
7.1 VB_CLKDIV Register
VB_CLKDIV register set the frequency of transfer clock when the buck-up register and port register are
transferred simultaneously.
bit
7
6
5
4
3
2
1
0
Field
DIV7
DIV6
DIV5
DIV4
DIV3
DIV2
DIV1
DIV0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
1
1
1
The interface circuit type for this register is type 1.
[bit7:0] DIV[7:0]: Transfer clock set bits for PREAD, PWRITE, BREAD, BWRITE
These bits set the transfer clock cycle used in the batch transfer of the backup register and of the port
register.
Equation of computing the register value: transfer clock = PCLK / (VB_CLKDIV + 2)
(Set these bits to a value that makes the frequency of the transfer clock used in BREAD/BWRITE and
PREAD/PWRITE 1 MHz or below.)