Cypress FM4 Series - Resets to Peripheral Circuit

CHAPTER 4: Resets
168 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
3.2.2 Resets to Peripheral Circuit
The bus resets (HRESET, PRESET0, PRESET1, and PRESET2) that are input to the peripheral circuit
are basically generated by all reset factors. Resetting of PRESET1 and PRESET2 can be controlled by
register settings.
The following provides reset factors for the bus resets.
Resets to Peripheral Circuit
 HRESET and PRESET0
Reset factors
− Power-on reset (PONR)
− Low-voltage detection reset (LVDH)
− INITX pin input (INITX)
− Software watchdog reset (SWDGR)
− Hardware watchdog reset (HWDGR)
− Clock Failure Detection reset (CSVR)
− Anomalous frequency detection reset (FCSR)
− Software reset (SRST)
− Deep standby transition reset (DSTR)
 PRESET1 and PRESET2
Reset factors
− Power-on reset (PONR)
− Low-voltage detection reset (LVDH)
− INITX pin input (INITX)
− Software watchdog reset (SWDGR)
− Hardware watchdog reset (HWDGR)
− Clock Failure Detection reset (CSVR)
− Anomalous frequency detection reset (FCSR)
− Software reset (SRST)
− APB bus resets (APBC1_PSR and APBC2_PSR)
− Deep standby transition reset (DSTR)
Notes:
− The peripheral circuit is essentially initialized with all reset factors. Depending on the
specifications of the peripheral circuit, there are registers that are initialized only with specific
causes. For the initialization conditions for registers, see the initialization conditions for the
registers described in the relevant chapter.
− For details on APB bus resets (APBC1_PSR and APBC2_PSR), see Chapter "Clock".