Cypress FM4 Series - Peripheral Reset Control Register 0 (MRST0)

CHAPTER 2-2: Clock Gating
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 95
4.2 Peripheral Reset Control Register 0 (MRST0)
This section explains the peripheral reset control register 0 (MRST0).
bit
31
30
29
28
27
26
25
24
Field
Reserved
EXBRST
Reserved
DMARST
Attribute
-
R/W
-
R/W
Initial value
-
0
-
0
bit
23
22
21
20
19
18
17
16
Field
Reserved
ADCRST[3:0]
Attribute
-
R/W
Initial value
-
0000
bit
15
14
13
12
11
10
9
8
Field
MFSRST[15:8]
Attribute
R/W
Initial value
0x00
bit
7
6
5
4
3
2
1
0
Field
MFSRST[7:0]
Attribute
R/W
Initial value
0x00
[bit31:27] Reserved: Reserved bits
Write 0 to these bits.
[bit26] EXBRST: Reset control for external bus interface
This bit controls the reset of the external bus interface only. When this bit is set to 1, the external bus
interface is reset to disable the operation of the external bus interface. For products to which the external
bus interface is not mounted, do not change this bit from the initial value. To release the reset status, be
sure to set this bit to 0 again.
bit
Description
0
Releases the reset of the external bus interface. (Initial value)
1
Executes the external bus interface reset.
When using the external bus interface, set EXBRST bit become 1 to execute external bus interface reset
and then this bit become 0 to release the reset. After the setting, set external bus control registers.
Note:
− The external bus interface reset control with the above register control cannot initialize the
registers of the external bus interface.
[bit25] Reserved: Reserved bit
Write 0 to this bit.
[bit24] DMARST: Reset control of DMAC
This bit controls reset of the DMAC unit. If this bit is set to 1, DMAC becomes a reset state, the DMA
transfer operation stops, and all the register settings are initialized. To release the reset state, be sure to
set this bit to 0 again.
bit
Description
0
Releases the DMAC reset. (Initial value)
1
Issues reset signal to DMAC.