CHAPTER 8: Interrupts
424 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
4.33 IRQ102 Batch Read Register (IRQ102MON)
The IRQ102 Batch Read Register (IRQ102MON) can read out at once the interrupts (interrupts of base
timer ch.12 to ch.15, GDC) assigned to exception no. 118.
Register configuration
Register function
[bit31:9] Reserved: Reserved bits
A reserved bit reads 0.
[bit8] GDCINT
Register by has the following features. Other than the following becomes a reserved bit “0” is read.
[bit7:0] BTINT
There is no interrupt request of source 1 (IRQ1) of base timer ch.15.
An interrupt request of source 1 (IRQ1) of base timer ch.15 has been made.
There is no interrupt request of source 0 (IRQ0) of base timer ch.15.
An interrupt request of source 0 (IRQ0) of base timer ch.15 has been made.
There is no interrupt request of source 1 (IRQ1) of base timer ch.14.
An interrupt request of source 1 (IRQ1) of base timer ch.14 has been made.
There is no interrupt request of source 0 (IRQ0) of base timer ch.14.
An interrupt request of source 0 (IRQ0) of base timer ch.14 has been made.
There is no interrupt request of source 1 (IRQ1) of base timer ch.13.
An interrupt request of source 1 (IRQ1) of base timer ch.13 has been made.
There is no interrupt request of source 0 (IRQ0) of base timer ch.13.
An interrupt request of source 0 (IRQ0) of base timer ch.13 has been made.
There is no interrupt request of source 1 (IRQ1) of base timer ch.12.
An interrupt request of source 1 (IRQ1) of base timer ch.12 has been made.
There is no interrupt request of source 0 (IRQ0) of base timer ch.12.
An interrupt request of source 0 (IRQ0) of base timer ch.12 has been made.
The respective details of interrupt factor 0 (IRQ0) and interrupt factor 1 (IRQ1) to be output from the base
timer vary depending on the base timer function used. For details, see Table 4-1.
There is no interrupt request of the GDC SafetyStream1.
An interrupt request of the GDC CommandSequencer has been made.