Cypress FM4 Series - Bus Architecture

CHAPTER 1: System Overview
24 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
1. Bus Architecture
This section explains the bus architecture.
For this family bus, AHB Bus Matrix circuit actualizes a multi-layer bus. Master and slave architectures
are shown below:
 Master
− Cortex-M4F CPU(I-code Bus, D-code Bus, System Bus)
− Ethernet/SD-Card/GDC
− DMAC
− DSTC
 Slave
− On-chip Flash Memory (MainFlash, WorkFlash)
− On-chip SRAM (SRAM0, SRAM1, SRAM2)
− External Bus
− USB ch.0/ch.1
− AHB-AHB Bus Bridge
− AHB-APB Bus Bridge (APB0 to APB2)
See Figure 1-1 for the bus block diagram.
Features
 RAM Architecture
This family divides the on-chip SRAM area into three separate SRAM (SRAM0, SRAM1, and SRAM2).
SRAM0 is connected to the I-Code bus and D-Code bus of the Cortex-M4 core. SRAM1 and SRAM2 are
connected to the System bus of the Cortex-M4 core. Also, SRAM0, SRAM1, and SRAM2 are connected
to DMAC and other bus masters. This allows for preventing conflicts to RAM by multiple bus masters
such as CPU and DMAC and allows for improving the performance.
Also, because the divided RAM address areas are serial, RAM area can be utilized to the maximum
extent.
 APB Extension Bus
APB1 and APB2 Peripheral Buses are APB extension bus that the following functions are originally added
based on AMBA3.0. (APB0 is not included.)
− Supporting Halfword (16 bits) and Byte(8 bits) Accesses
For supported registers, halfword access and byte access are enabled.
See A. Register Map in Appendixes for the supported registers.
− Adding Read-Modify-Write (RMW) Signal
HMASTLOCK signal in bit-band operations is used to generate.
RMW signal is a signal added to prevent that an unrelated flag is cleared mistakenly in
read-modify-write process of bit-band operations.
The corresponding flag reads 1 in read during the read-modify-write process and is designed to
ignore 1 write.
This prevents any unrelated flag from being mistakenly cleared in the next write when the flag is
set immediately after the read in the sequence from read to modify to write.
For the corresponding flags and registers, it is described that "regardless of bit values, 1 can be
read in "Read-Modify-Write".