Cypress FM4 Series - Peripheral Clock Gating Configuration

CHAPTER 2-2: Clock Gating
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 85
2. Peripheral Clock Gating Configuration
This section explains the configuration of the Peripheral Clock Gating.
Block Diagram
Figure 2-1 shows the system configuration of Peripheral Clock Gating.
Figure 2-1 Block Diagram of Peripheral Clock Gating
Clock Generation Unit/
Reset Generation Unit
Base Clock(HCLK)
Peripheral Clock Gating
Control Unit
Peripheral Function(01)
Colck
Reset
*3
Peripheral Function(0n)
Colck
Reset
*3
HRESET
G01
R01
R0n
Peripheral Function(11)
Colck
Reset
*3
Peripheral Function(1n)
Colck
Reset
*3
R11
R1n
Peripheral Function(21)
Colck
Reset
*3
Peripheral Function(2n)
Colck
Reset
*3
R21
R2n
PRESET1
PRESET2
PCLK1
PCLK2
G0n
G11
G1n
G21
G2n
G01
G0n
G11
G1n
G21
G2n
R01
R0n
R11
R1n
R21
R2n
HCLK Operation
PCLK1 Operation
PCLK2 Operation
Operation C lock
Setting Reset
Clock Control Output
0b0 : Clock Gating
1b1 : Clock Supply
Reset Control Output
0b0 : Reset released
1b1 : Reset enabled
*1
*1
*1
*1
*1
*1
*2
*2
*2
*2
*2
*2
*1: Gates the operation clocks of peripheral functions
*2: Resets peripheral functions
*3: At High-level signal input: Reset enabled, At Low-level signal input: Reset released