Cypress FM4 Series - Control Functions of DSTC; Control of SW Transfer; DESTP Register; DSTC Internal Block Diagram

CHAPTER 11: DSTC
522 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
3.2 Control Functions of DSTC
This section explains the control functions of the DSTC.
3.2.1 DSTC internal Block Diagram
Figure 3-5 illustrates the connection between control blocks and control registers (shaded rectangles) in
the DSTC that can be accessed from the CPU. The CPU starts DSTC transfer and controls end
notifications via accesses to control registers. The following sections explain the operations of each block
and the function overview of each register shown in the DSTC internal block diagram. For details of
register functions, see "5. Registers and Descriptors of DSTC".
Figure 3-5 DSTC Internal Block Diagram
DREQENB[n]
Register
DREQ[n] from peripheral
DQMSK[n] Register
Arbiter 1
ERINT
interrupt
signal
SWDESP bits in
SWTR Register
Software transfer request
from CPU
Arbiter 2
HWDESP[n] Register
HWINT[n]
interrupt
signal
SWINT
interrupt
signal
SWPR bit in CFG
Register
HWINT[n] Register
SWST bit in
SWTR Register
SWINTE bit in
CFG Register
SWREQ bit in
SWTR Register
MONERS Register
ERINTE bit in
CFG Register
HWINTCLR[n] Register
DQMSKCLR[n]
Register
DES on memory
DES read
skip buffer
RBDIS bit in
CFG Register
DESTP Register
Memory I/F
CMD Register
Transfer
engine
HWDESPBUF
3.2.2 DESTP Register
The DESTP (DES top address) Register is a register specifying the start address of the DES area on the
memory. Specify the start address when doing the initial settings. The DSTC refers to the DES located at
the address of "DESTP + DESP" and executes a transfer.
3.2.3 Control of SW Transfer
To issue a Start Trigger of the SW Transfer, write the DESP value of the DES to be started to SWDESP
(Software DES pointer) in the SWTR (Software trigger) Register. If a Chain Start is executed during the
SW Transfer, SWDESP is updated by the DSTC to the value of DESP used in the Chain Start. The value
of SWDESP is sent to Arbiter 2 in Figure 3-5 as a transfer request.
The SWREQ (Software request) bit in the SWTR Register is a read-only bit indicating whether the
execution of the SW Transfer is pending, or the SW Transfer as well as the Chain Start transfer are being
executed. A write access (Start Trigger) to the SWTR Register sets the SWREQ bit to 1. If the SW
Transfer ends normally, abnormally, or is waiting for a Start Trigger, SWREQ is reset to 0.
A SW Start trigger can be issued only after the current SW Transfer has ended. If the SWREQ bit is 1, a
write access to the SWTR Register is ignored.
The SWST (Software status) bit in the SWTR Register is a read-only bit for sending the SW transfer end
notification to the CPU. In the interrupt flag set is specified in the CHRS in the DES of SW Transfer, or in
the DES started by the Chain Start from the SW Transfer. If the SW Transfer ends normally, SWST is set
to 1. SWST can be cleared to 0 by sending the SWCLR command to the CMD Register.
If the SWST bit has been set to 1, the SWINT interrupt can be enabled by writing 1 to the SWINTE bit in
the CFG Register. In the case of (SWINTE==1) & (SWST==1), the SWINT interrupt signal for the NVIC is
asserted.