Cypress FM4 Series - WKUP Pin Input Level Register (WILVR)

CHAPTER 6: Low Power Consumption Mode
238 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
8.7 WKUP Pin Input Level Register (WILVR)
The WKUP Pin Input Level Register selects the respective valid levels for the WKUP1 to WKUP5 pin
inputs having occurred in a deep standby mode.
Bit
7
6
5
4
3
2
1
0
Field
Reserved
WUI5LV
WUI4LV
WUI3LV
WUI2LV
WUI1LV
Attribute
-
R/W
R/W
R/W
R/W
R/W
Initial value
000
0
0
0
0
0
[bit7:5] Reserved: Reserved bits
These bits always read 0b00.
Writing a value to these bits has no effect on operation.
[bit4:0] WUI5LV to WUI1LV: WKUPx pin input level select bits
These bits select the respective valid levels for the WKUPx pin inputs.
Bit
Description
0
A return request is made if the WKUPx pin input is L level. [initial value]
1
A return request is made if the WKUPx pin input is H level.
Notes:
− L level is the only valid level of the WKUP0 pin input for making a return request.
For example, with the WUI1LV bit set to 0, if L level is input to the WKUP1 pin, as soon as the
CPU transits to a deep standby mode, it returns to a Run mode.
− This register is not initialized by the deep standby transition reset.