Cypress FM4 Series - Clock Generation Unit Usage Precautions

CHAPTER 2-1: Clock
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 79
6. Clock Generation Unit Usage Precautions
This section explains the precautions for using the clock generation unit.
 The oscillation stabilization wait time of main clock and sub clock oscillators
Because the stabilization wait time of main clock/sub clock oscillator depends on the oscillator type
(crystal, ceramic, etc.), the oscillation stabilization wait time suitable for the oscillator type must be
selected.
 Changing the frequency division under stabilized PLL oscillation
When the PLL frequency division ratio is changed after stabilization of PLL oscillation, stop the PLL
oscillation once, change the frequency division ratio, and then re-enable the PLL oscillation.
 Peripherals independent of clock control by the clock generation unit
The following peripherals run independently of clock control by the clock generation unit.
For information about how to handle each operating clock, see the following chapter.
− USB operating clock generation unit : See Chapter USB Clock Generation in Communication Macro
Part.
− Clock supervisor : See Chapter Clock supervisor.
− Watchdog timer: See Chapter Watchdog Timer in Timer Part.
− Watch counter: See Chapter Watch Counter in Timer Part.
− Real-time clock: See Chapter Real-Time Clock in Timer Part.
− CAN prescaler: See Chapter CAN Prescaler in Communication Macro Part.
− GDC: See GDC Part.
 Setting the oscillation stabilization wait time
Set the oscillation stabilization wait time of the main clock, sub clock, and PLL oscillators with relevant
oscillation stabilization wait time setup registers, and then enable each oscillator.
Do not change the oscillation stabilization wait time while waiting for oscillation to stabilize.
 Checking main clock oscillation while using the main PLL clock
It is prohibited to stop main clock oscillation while using PLL oscillation.
 Switching clock modes
Clock modes can be switched by changing the RCS[2:0] bits of the SCM_CTL register.
To switch clock modes, take the following steps:
1. Set the oscillation stabilization wait time of each oscillator.
2. Set the oscillation enable bit of the desired clock (SCM_CTL:xxxE) to 1.
3. Check the oscillation stable bit of the desired clock (SCM_CTL:xxxRDY) to 1.
4. Switch SCM_CTL:RCS[2:0].
5. Wait until SCM_STR:RCM[2:0] = SCM_CTL:RCS[2:0].
 Correlation between the clock mode switching and the oscillation stable bit
The timings when the oscillation stable bit (SCM_STR:xxxRDY) turns to "1" vary for the following clock
mode switching.
− When switching from the high-speed CR run, main run, or PLL run to another clock mode:
Setting SCM_CTL:xxxE to 1 can start the oscillation stabilization wait time. You can check that
SCM_STR:xxxRDY is 1 after the oscillation stabilization wait time has elapsed.
− When switching from the low-speed CR run or sub run to the high-speed CR run, main run, or PLL
run:
Even if SCM_CTL:MOSCE (or PLLE) set to 1, oscillation of main clock does not start. To start the
main clock (or high-speed CR or PLL) oscillation stabilization wait time, SCM_CTL:RCS [2:0]
must be switched after setting SCM_CTL:MOSCE (or PLLE) to 1. After the oscillation stabilization
wait time has elapsed, you can check that SCM_STR:xxxRDY is 1.