Cypress FM4 Series - Base Clock Prescaler Register (BSC_PSR)

CHAPTER 2-1: Clock
62 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
5.3 Base Clock Prescaler Register (BSC_PSR)
The BSC_PSR sets the frequency division ratio of the base clock.
Register configuration
bit
7
6
5
4
3
2
1
0
Field
Reserved
BSR
Attribute
-
R/W
Initial value
-
000
Register functions
[bit7:3] Reserved: Reserved bits
0b00000 is read from these bits.
Set these bits to 0b00000 when writing.
[bit2:0] BSR: Base clock frequency division ratio setting bits
bit2
bit1
bit0
Description
0
0
0
1/1 [Initial value]
0
0
1
1/2
0
1
0
1/3
0
1
1
1/4
1
0
0
1/6
1
0
1
1/8
1
1
0
1/16
1
1
1
Setting is prohibited
Note:
− This register is not initialized by software reset.