CHAPTER 11: DSTC
570 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
5.11 DQMSK[n] Register
The DQMSK[n] Register indicates whether the HW Start transfer request is being suppressed.
Register configuration
Attribute
(applicable to all areas)
Initial value
(applicable to all areas)
Register function
The DQMSK[n] Register is a read-only register. The write access to this register is ignored. That this
register is "1" indicates the HW Start transfer request (DREQ[n]) to the DSTC is being suppressed. If one
of the following conditions is met, the DSTC sets DQMSK[n] to "1" and suppresses transfer requests.
− A transfer error has occurred at a transfer on HW channel n.
− The CPU has issued a standby transition command to the CMD Register.
− DMSET in the DES for the transfer on HW channel n is "1" and the DSTC has executed a DES
close process.
If one of the following conditions is met, the DSTC clears DQMSK[n] to "0" and releases the suppression
of transfer requests.
− "1" has been written to the DQMSKCLR[n] Register.
− The CPU has issued a standby transition command to the CMD Register.
bit[255:0] DQMSK[255:0] (DMA request mask)
Causes no operation to be executed.
Indicates that the DREQ[n] signal from the peripheral is not being suppressed.
Indicates that the DREQ[n] signal from the peripheral is being suppressed.
If the DSTC installed in a product supports HW-128 channels, the DQMSK[255:128] bits are a reserved
area whose value is fixed at "0".
If the DSTC installed in a product supports HW-64 channels, the DQMSK[255:64] bits are a reserved
area whose value is fixed at "0".
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