CHAPTER 11: DSTC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 523
3.2.4 Control of HW Transfer
If a peripheral makes a transfer request (assertion of DREQ[n]), the DSTC starts the HW Transfer. The
DSTC controls the HW Transfer on a transfer channel using the following registers whose number
corresponds to the number of transfer channels. The CPU does the initial settings of those registers
before a peripheral makes a transfer request. In addition, the CPU clears registers according to the
progress of a transfer.
DREQENB[n] Register
The DREQENB[n] (DMA request enable) Register determines whether HW channel n is used in the initial
settings. Write 1 to the DREQENB[n] Register to use HW channel n. Write 0 to the DREQENB[n] Register
to not use HW channel n. If the DREQENB[n] Register is 0, the interrupt signal (DREQ[n]) of a peripheral
connected to the DSTC is ignored. The value of the DREQENB[n] Register is not modified by the DSTC.
The value of the DREQENB[n] Register determines which of the interrupt signal from a peripheral and
HWINT[n] from the DSTC is selected as an interrupt signal connected to the NVIC. For its details, see "2
DSTC Operations Overview and DSTC System Configuration".
DQMSK[n] Register and DQMSKCLR[n] Register
The DQMSK[n] (DMA request mask) Register is a read-only register. This register is 1 indicates that the
HW Start request (DREQ[n]) to the DSTC is being suppressed. If one of the following conditions is met,
the DSTC sets DQMSK[n] to 1 and suppresses the transfer request of the HW channel corresponding to
DQMSK[n].
− A transfer error has occurred at a HW Transfer on HW channel n.
− The CPU has issued a standby transition command to the CMD Register.
− DMSET in the DES for the transfer on HW channel n is 1 and the DSTC has executed a DES close
process.
After the CPU has rebuilt the DES and the HW transfer has become ready to start, the suppression of the
HW Start transfer request to the DSTC can be released by the CPU. If 1 is written to the DQMSKCLR[n]
(DMA request mask clear) Register, the DQMSK[n] Register is cleared to 0 and the succeeding HW
transfer request (DREQ[n]) is recognized.
HWDESP[n] Register
The HWDESP[n] (Hardware DES pointer) Register sets the DESP of the DES that the DSTC refers to
and executes at a transfer request of HW channel n. Set this register before making an HW transfer
request.
If an HW Start trigger is issued, the DSTC starts a transfer referring to the DES of the DESP set in the
HWDESP[n] Register. The DSTC stores the DESP value of the HWDESP[n] Register in HWDESPBUF in
Figure 3-5 before using it. In a Chain Start, the value stored in HWDESPBUF is updated to the DESP
value set after the Chain Start. The value of the HWDESP[n] Register cannot be modified by the DSTC.
If HW Start requests of channel n are made successively, the DSTC uses the DESP value stored in
HWDESPBUF, but not the DESP value of the HWDESP[n] Register. Therefore, if the values of the
HWDESP[n] Register are modified via the CPU, invalidate the value stored in HWDESPBUF. The DESP
value of HWDESPBUF can be invalidated by modifying the value of the RBDIS bit in the CFG Register.
For its details, see 5.5 CFG Register.
HWINT[n] Register and HWINTCLR[n] Register
The HWINT[n] (Hardware transfer interrupt) Register is a read-only register for sending the HW transfer
end notification to the CPU. The interrupt flag set is specified in the DES started by the HW Start, or
CHRS in the DES started by the Chain Start after the DES started by the HW Start. If the HW transfer
ends normally, HWINT[n] is set to 1. The HWINT[n] Register can be cleared to 0 by writing 1 to the
HWINTCLR[n] Register. If the HWINT[n] Register is set to 1, the HW transfer completion interrupt signal
from the DSTC (HWINT[n]) for the NVIC is asserted.
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