Cypress FM4 Series - Non Maskable Interrupt Factor Register (NMIRR)

CHAPTER 9: External Interrupt and NMI Control Sections
450 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
4.6 Non Maskable Interrupt Factor Register (NMIRR)
The NMIRR Register indicates that a non maskable interrupt (NMI) request is detected.
Register configuration
bit
15
1
0
Field
Reserved
NR
Attribute
-
R
Initial value
-
0
Register functions
[bit15:1] Reserved: Reserved bits
The read value is undefined.
They have no effect in write mode.
[bit0] NR: NMI interrupt request detection bit
The NR bit corresponds to NMIX pin.
bit
Function
0
Detects no NMI interrupt request.
1
Detects an NMI interrupt request.
Writing
No effect on operation
Note:
− When the I/O port which is mapped to NMI input pin is changed to GPIO or other peripheral
function from NMI (write EPFR00.NMIS = 1), input level of the I/O port should be held high level,
and change the I/O port. Internal NMI signal is tied to high level in case of the I/O port is selected
to GPIO or other peripheral function. Therefore, when input level of the I/O port is low, to change
the I/O port from GPIO or other peripheral function to NMI, is caused to change of internal NMI
signal high to low. So, falling edge will be detected, NMI request occurred.