Cypress FM4 Series - Mode 0 Register to Mode 7 Register (MODE0 to MODE7)

CHAPTER 14: External Bus Interface
804 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
6.1 Mode 0 Register to Mode 7 Register (MODE0 to MODE7)
The MODE0 to MODE7.registers set the operation mode of SRAM/Flash memory access.
bit
31
30
29
28
27
26
25
24
Field
Reserved
Attribute
-
Initial value
-
bit
23
22
21
20
19
18
17
16
Field
Reserved
Attribute
-
Initial value
-
bit
15
14
13
12
11
10
9
8
Field
Reserved
MOEXEUP
MPXCSOF
MPXDOFF
Reserved
ALEINV
MPXMODE
Attribute
-
R/W
R/W
R/W
-
R/W
R/W
Initial value
-
0
0
0
-
0
0
bit
7
6
5
4
3
2
1
0
Field
SHRTDOUT
RDY
PAGE
NAND
WEOFF
RBMON
WDTH
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
00*
*: The initial value of these bits is 01 only for MODE4 register.
[bit31:14] Reserved: Reserved bits
The read value is undefined.
Set this bit to 0 when writing.
[bit13] MOEXEUP: MOEX EUP
This bit is used to select how to set the MOEX width.
bit
Description
0
MOEX width is set with RACC-RADC (Initial value).
1
MOEX width is set with FRADC.*
*: This function cannot be used combined with the page read function.
Note:
− See Reference Information for specific operations.
[bit12] MPXCSOF: MPX CS OF
This bit is used to select a CS assertion from the start of accessing to the end of address output (ALC
cycle period) in multiplex mode.
bit
Description
0
Asserts MCSX in ALC cycle period (Initial value).
1
Does not assert MCSX in ALC cycle period.
Note:
− See Reference Information for specific operations.