Cypress FM4 Series - High-Speed CR Oscillation Frequency Division Setup Register (MCR_PSR)

CHAPTER 2-3: High-Speed CR Trimming
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 125
5.1 High-speed CR Oscillation Frequency Division Setup Register
(MCR_PSR)
The MCR_PSR register sets the frequency division ratio of high-speed CR oscillation.
A divided clock can be input in base timer.
Register configuration
bit
7
6
5
4
3
2
1
0
Field
Reserved
CSR
Attribute
-
R/W
Initial value
-
001
Register functions
[bit7:3] Reserved : Reserved bits
"0b00000" is read from these bits.
Set these bits to "0b00000" when writing.
[bit2:0] CSR: High-speed CR oscillation frequency division ratio setting bits
bit2
bit1
bit0
Description
0
0
0
1/4
0
0
1
1/8 [Initial value]
0
1
0
1/16
0
1
1
1/32
1
0
0
1/64
1
0
1
1/128
1
1
0
1/256
1
1
1
1/512