CHAPTER 4: Resets
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 173
4.1 Reset Factor Register (RST_STR: ReSeT STatus Register)
The Reset Factor Register (RST_STR) shows the factors of resets that have just occurred. All bits of the
RST_STR are initialized by a power-on reset, a low-voltage detection reset or a deep standby reset. It is
not initialized by any other reset. All bits of the RST_STR are cleared to “0” by reading this register.
After initializing, until it has been read, this register stores all reset factors that have been generated.
Note: The initial value is the value upon power-on.
[bit15:9] Reserved: Reserved bits
The read value is undefined.
These bits have no effect when written.
[bit8] SRST: Software reset flag
Indicates a reset that is generated by writing "1" to Cortex-M4 internal reset control register
(SYSRESETREQ bit).
When a software reset is generated, SRST is enabled (SRST = 1).
A software reset has not been issued.
A software reset has been issued.
[bit7] FCSR: Flag for anomalous frequency detection reset
Indicates a reset when an anomalous frequency is detected in the main oscillation.
When the frequency of the main oscillation is outside of a given setting, a reset is issued and FCSR is
enabled (FCSR = 1).
An anomalous frequency detection reset has not been issued.
An anomalous frequency detection reset has been issued.
[bit6] CSVR: Clock failure detection reset flag
Indicates a reset when a failure is detected in the main or sub oscillation.
If a stop is detected, a reset is issued and CSVR is enabled (CSVR = 1).
A clock failure detection reset has not been issued.
A clock failure detection reset has been issued.
Note: Please refer to Chapter "Clock supervisor" for the method of judging whether the main oscillation or
the sub oscillation broke down.
[bit5] HWDT: Hardware watchdog reset flag
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