CHAPTER 2-2: Clock Gating
88 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
3.1 Peripheral Clock Control Procedures
This section explains the control procedures of supplying and stopping peripheral clocks.
Clock Supply Procedures
The settings of the bus clocks and the peripheral clocks are reset to the initial values immediately after
the bus reset release. So, for the clocks of peripheral functions which have been stopped in the initial
state, set the clock supplies conforming to the procedures in Figure 3-1.
Figure 3-1 Clock Supply Procedures
Bus Reset Releasing
Supply Setting of Peripheral Clocks
(Setting Change of CKEN* Registers)
CKEN* Read Value = Written Value ?
No
Yes
Access to Target Macros Enabled.
Bus Clock Setting
*:Indicates CKEN0, CKEN1, and CKEN2
1. Bus clock setting
Execute the setting of each bus clock by using the register of the clock generation part.
For the setting details, see Chapter Clock.
2. Supply setting of peripheral clocks
Change the setting of the bit corresponding to the peripheral function to which the clock is to be supplied
for peripheral clock control registers (CKEN0, CKEN1, and CKEN2) of the clock control in the clock gating
state of the initial state.
3. Set value confirmation of peripheral clock control register
The peripheral clock registers (CKEN0, CKEN1, and CKEN2) updates the register value to the written
value at the step of starting the clock supply to the peripheral function to which the setting is changed.
Be sure to start the access to the peripheral function after setting a change in the above-mentioned Item
2, reading this register, and then confirming the agreement with the written value because an access to
peripheral function is invalid at clock gating.
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