Cypress FM4 Series - Clock Stabilization Wait Time Register (CSW_TMR)

CHAPTER 2-1: Clock
68 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
5.9 Clock Stabilization Wait Time Register (CSW_TMR)
The CSW_TMR sets the stabilization wait time of the main/sub clock.
Register configuration
bit
7
6
5
4
3
2
1
0
Field
SOWT
MOWT
Attribute
R/W
R/W
Initial value
0000
0000
Register functions
[bit7:4] SOWT: Sub clock stabilization wait time setup bits
bit7
bit6
bit5
bit4
Description
0
0
0
0
2
10
/ FCRL : Approx. 10.3 ms * [Initial value]
0
0
0
1
2
11
/ FCRL : Approx. 20.5 ms *
0
0
1
0
2
12
/ FCRL : Approx. 41 ms *
0
0
1
1
2
13
/ FCRL : Approx. 82 ms *
0
1
0
0
2
14
/ FCRL : Approx. 164 ms *
0
1
0
1
2
15
/ FCRL : Approx. 327 ms *
0
1
1
0
2
16
/ FCRL : Approx. 655 ms *
0
1
1
1
2
17
/FCRL : Approx.1.31s *
1
0
0
0
2
18
/ FCRL : Approx. 2.62s *
1
0
0
1
2
19
/ FCRL : Approx. 5.24s *
1
0
1
0
2
20
/ FCRL : Approx. 10.48s *
1
0
1
1
2
21
/ FCRL : Approx. 20.96s *
Other than the above
Setting is prohibited.
*: When FCRL=100 kHz
[bit3:0] MOWT: Main clock stabilization wait time setup bits
bit3
bit2
bit1
bit0
Description
0
0
0
0
2
1
/ FCRH : Approx. 500 ns * [Initial value]
0
0
0
1
2
5
/ FCRH : Approx. 8 µs *
0
0
1
0
2
6
/ FCRH : Approx. 16 µs *
0
0
1
1
2
7
/ FCRH : Approx. 32 µs *
0
1
0
0
2
8
/ FCRH : Approx. 64 µs *
0
1
0
1
2
9
/ FCRH : Approx. 128 µs *
0
1
1
0
2
10
/ FCRH : Approx. 256 µs *
0
1
1
1
2
11
/ FCRH : Approx. 512 µs *
1
0
0
0
2
12
/ FCRH : Approx. 1.0 ms *
1
0
0
1
2
13
/ FCRH : Approx. 2.0 ms *
1
0
1
0
2
14
/ FCRH : Approx. 4.0 ms *
1
0
1
1
2
15
/ FCRH : Approx. 8.0 ms *
1
1
0
0
2
17
/ FCRH : Approx. 33.0 ms *
1
1
0
1
2
19
/ FCRH : Approx. 131 ms *
1
1
1
0
2
21
/ FCRH : Approx. 524 ms *
1
1
1
1
2
23
/ FCRH : Approx. 2.0 s *
*: When FCRH=4 MHz
Notes:
− Set each oscillation stabilization wait time before enabling each oscillation enable bit (SOSCE,
MOSCE) of the SCM_CTL register.
If you change MOWT or SOWT bit while waiting for oscillation stability of each oscillator, each
oscillation stabilization wait time is not guaranteed.
− This register is not initialized by software reset.