Cypress FM4 Series - Hardware-Demand Transfer

CHAPTER 10: DMAC
464 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
3.3 Hardware-Demand Transfer
This section explains Hardware-Demand transfer.
Hardware-Demand transfer is used when performing DMA transfer by the transfer request signal from the
Peripherals of USB, MFS and ADC.
Hardware-Demand transfer is a method used to receive the transfer request signal from Peripherals on a
signal level. If the transfer request signal is on High level, transfer is executed. If the transfer request
signal is on Low level, no transfer is executed. Transfer is executed by setting the output of the interrupt
signal from each Peripheral to High level (with interrupt request) when transfer data exists, or to Low level
(without transfer request) when no transfer data exists.
In the case of Hardware-Demand transfer, always specify 1 (BC=0) as the number of blocks.
Figure 3-3 shows an example of the operation of Hardware-Demand transfer. In this example, the
following settings apply. The settings of the addresses of the transfer source and transfer destination as
well as the transfer data width are omitted.
− Transfer mode: Hardware-Demand transfer
(ST=0, IS= Peripheral at the transfer request source, MS=10)
− Transfer data size: Number of blocks = 1, Number of transfers = 3 (BC=0, TC=2)
Figure 3-3 Example of Operation of Hardware-Demand Transfer
Transfer action
TC(reload) 2 1 0
BC(reload) 0
Start request from CPU
Transfer normal end
Transfer request
1st Transfer request from Peripheral
2
0
The operation of Hardware-Demand transfer is as follows:
The start of the operation is instructed by specifying the transfer content from CPU. DMAC waits for a
transfer request from the Peripheral. After receiving the transfer request, it performs one transfer and then
waits for the next transfer request. During the wait period, a Transfer Gap is generated. Every time a
transfer request is received, it performs the same operation for the number of transfers (TC+1). The total
number of transfers to be performed is (TC+1). Match the number of transfer requests from the Peripheral
and the number of DMAC transfers (TC+1). Once all of the transfers are completed, DMAC notifies CPU
of the completion.