Cypress FM4 Series - Interrupt Clear Register (INT_CLR)

CHAPTER 2-1: Clock
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 75
5.16 Interrupt Clear Register (INT_CLR)
The INT_CLR clears interrupt factors.
Register configuration
bit
7
6
5
4
3
2
1
0
Field
Reserved
FCSC
Reserved
PCSC
SCSC
MCSC
Attribute
-
W
-
W
W
W
Initial value
-
0
-
0
0
0
Register functions
[bit7:6] Reserved: Reserved bits
0b00 is read from these bits.
Set these bits to 0b00 when writing.
[bit5] FCSC: Anomalous frequency detection interrupt factor clear bit
bit
Description
When 0 is
written
The FCS interrupt factor is not affected by the written value.
When 1 is
written
Clears the FCS interrupt factor.
When read
The fixed value 0 is read.
[bit4:3] Reserved: Reserved bits
0b00 is read from these bits.
Set these bits to 0b00 when writing.
[bit2] PCSC: PLL oscillation stabilization wait completion interrupt factor clear bit
bit
Description
When 0 is
written
The PLL oscillation stabilization wait completion interrupt factor is not affected by the written
value.
When 1 is
written
Clears the PLL oscillation stabilization wait completion interrupt factor.
When read
The fixed value 0 is read.
[bit1] SCSC: Sub clock oscillation stabilization wait completion interrupt factor clear bit
bit
Description
When 0 is
written
The sub clock oscillation stabilization wait completion interrupt factor is not affected by the
written value.
When 1 is
written
Clears the sub clock oscillation stabilization wait completion interrupt factor.
When read
The fixed value 0 is read.