CHAPTER 6: Low Power Consumption Mode
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 223
5.2 Operations in Deep Standby Stop Mode
In deep standby stop mode, all oscillators stop. All functions stop operating except for the Low Voltage
Detection Circuit. The power supply for CPUs, on-chip Flash memory, SRAM0/1/2* and peripherals
excluding the RTC, the HDMI-CEC/Remote Control Reception, the Low Voltage Detection Circuit and
GPIO are turned off inside the chip.
Functions of Deep Standby Stop Mode
CPU and on-chip memory
In deep standby stop mode, the CPU clock supplied to the CPU, the AHB bus clock supplied to the
on-chip memory and the DMA controller stop, and the power supply for the CPU, the on-chip Flash
memory and SRAM0/1/2* is turned off. Data in the registers of the CPU and that in SRAM0/1/2 is not
retained*. Data in the on-chip Flash memory is retained. In addition, the debug function stops and its
power supply is turned off.
*: Data in SRAM2 can be retained.
If the setting for retaining data in SRAM2 is done, the power supply for SRAM2 is turned on.
Peripherals
In deep standby stop mode, all APB bus clocks stop, and the power supply for all resources, except for
the RTC, the HDMI-CEC/Remote Control Reception, the Low Voltage Detection Circuit and the GPIO, is
turned off.
Oscillator clocks
All oscillator clocks stop.
Resets and WKUP pin input
Resets and WKUP pin input can be used for returning from deep standby stop mode.
Pin state
The SPL bit in the Standby Mode Control Register (STB_CTL) can control whether an external pin
switches to a GPIO in deep standby stop mode or changes to high impedance state.
Procedure for Setting Deep Standby Stop Mode
Execute the following procedure to make the CPU transit to deep standby stop mode.
1. Write 0 to the RTCE bit in the RTC Mode Control Register (PMD_CTL).
2. Write 0x1ACC, 1 and 0b10 to the KEY bits, DTSM bit and STM bits in the Standby Mode Control
Register (STB_CTL) respectively. Set the state of each pin in deep standby stop mode by using the
SPL bit.
3. Write 1 to the SLEEPDEEP bit in the Cortex-M4F System Control Register.
4. Execute the WFI instruction or the WFE instruction.
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