CHAPTER 8: Interrupts
354 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
1. Overview
The Cortex-M4 CPU core is equipped with the Nested Vectored Interrupt Controller (NVIC) inside the
core. The NVIC supports reserved system exceptions and 128 peripheral interrupts, and can set the
priority order of 16 interrupt priority levels (with a built-in 4-bit register). This section explains interrupt
signals from peripheral functions installed in the microcontroller and the connection between the NVIC
and the interrupt signals.
2. Configuration
Block Diagram
Figure 2-1 Connection between Interrupt Signals and NVIC
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