Cypress FM4 Series - Configuration B Register (DMACB)

CHAPTER 10: DMAC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 497
5.4 Configuration B Register (DMACB)
This section explains configuration B register (DMACB).
bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Field
Reserved
MS[1:0]
TW[1:0]
FS
FD
RC
RS
RD
EI
CI
SS[2:0]
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
00
00
00
0
0
0
0
0
0
0
000
bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Field
Reserved
EM
Attribute
R/W
R/W
Initial Value
000000000000000
0
[bit31:30] Reserved: Reserved bits
"0" is read out from these bits.
When writing these bits, set them to "0".
[bit29:28] MS[1:0] : Mode Select
These bits select the transfer mode.
bit
Function
00
Block transfer mode (Initial value)
01
Burst transfer mode
10
Demand transfer mode
11
Reserved
[bit27:26] TW[1:0] : Transfer Width
These bits specify the bit width of transfer data.
bit
Function
00
Byte (8 bits) (Initial value)
01
Half-word (16 bits)
10
Word (32 bits)
11
Reserved
[bit25] FS : Fixed Source
This bit specifies whether to increment or fix the transfer source address.
bit
Function
0
Increments the transfer source address according to TW[1:0]. (Initial value)
1
Fixes the transfer source address.
[bit24] FD : Fixed Destination
This bit specifies whether to increment or fix the transfer destination address.
bit
Function
0
Increments the transfer destination address according to TW[1:0]. (Initial value)
1
Fixes the transfer destination address.