Cypress FM4 Series - Lists of Interrupts

CHAPTER 8: Interrupts
358 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
3. Lists of Interrupts
This section shows a list of sources of exceptions and interrupt sources input to the NVIC, a list of
interrupts that can be transferred by the DMA transfer by the DMAC, and a list of interrupts that can be
transferred by the DMA transfer by the DSTC.
List of Exceptions and Interrupts
Table 3-1 (TYPE1-M4, TYPE2-M4, TYPE3-M4, TYPE5-M4, TYPE6-M4 Products) and Table 3-2
(TYPE4-M4 Product) shows a list of sources of exceptions and interrupt to be input to the NVIC. Below
are details of columns in the table.
Exc no.
NVIC exception number
IRQ no.
Peripheral interrupt number (number = Exc no. – 16)
Vector offset
Storage offset address of the vector that an interrupt refers to
Bit
This indicates the number of a bit in a Batch Read Register (IRQxxxMON or EXC02MON) from which an
interrupt source is read out. In the case of a single IRQ having multiple bit numbers. Multiple sources are
aggregated by logical OR, and a source can be read output from its corresponding bit. In the case of a
single IRQ having only bit number “0”, no multiple sources are aggregated by logical OR. “-“ in this
column indicates that there is no Batch Read Register for that exception or interrupt.
Bit number not listed is I have a reserved bit.
DMAC
“-“, as the described value, indicates that this interrupt does not support the DMA transfer by the DMAC.
“A number“, as the described value, indicates that this interrupt support the DMA transfer by DMAC. And,
“A number“, shows the bit number in the DRQSEL Register. The DRQSEL[n] register setting determines
the connection of SEL1 in the Figure 2-1. In case of DRQSEL[n]=0, the described interrupt is connected.
In case of DRQSEL[n]=1, the described interrupt is not connected.
DSTC
“-“, as the described value, indicates that it is not supported with DMA transfer by DSTC.
“A number“, as the described value, indicates that this interrupt support the DMA transfer by DSTC, and
this interrupt is generated by Combined type peripheral. “A number“, shows the bit number in the
DREQENB[n] Register. The DREQENB[n] register setting determines the connection of SEL2 in the
Figure 2-1. In case of DREQENB[n]=0, the described interrupt is connected. In case of DREQENB[n]=1,
the HWINT[n] from the DSTC is connected.
“*”, as the described value, indicates that the HWINT[n] from the DSTC is connected. This is Separated
type peripheral.
Exception source and interrupt source
This column contains exception sources and interrupt sources. Some interrupts have multiple sources.
Such interrupt sources of a peripheral function are aggregated by logical OR. Even if only one interrupt
source from a peripheral source is shown, such peripheral function may have multiple interrupt sources
aggregated by logical OR. For details, refer to the respective details of peripheral functions.